In a current gate first high-k/metal gate (HKMG) integration process the gate electrode stack is fabricated by forming a high-k dielectric layer and work function layer on a substrate, followed by forming a layer of polycrystalline silicon (poly Si) on the work function layer. As illustrated in FIG. 1, gate 103 is formed by depositing high-k dielectric layer 105 on substrate 101, followed by forming work function layer 107 on high-k dielectric layer 105. Work function layers commonly include tantalum (Ta), tungsten (W), titanium nitride (TiN), or tantalum nitride (TaN). Poly Si layer 109 is then formed on work function layer 107, followed by patterning and etching spacers 111 on opposite sides of gate 103, and formation of source/drain regions 113. However, during the poly Si deposition and subsequent anneals, a thin dielectric interface 115 containing silicon nitride (Si3N4) and/or silicon dioxide (SiO2) is formed between work function layer 107 and poly Si layer 109, produced by the reaction of silicon (Si) and nitrogen and/or oxygen present on the surface of the work function layer, for example, on the surface of TiN. This specific metal/Si dielectric interface is the only metal semiconductor/interface that does not become silicided during processing. It prevents stable, reproducible and low-resistance interface connections, resulting in a poor high-frequency device performance. Although the metal/Si dielectric interface might be avoided in a replacement gate process, in a gate first technology this problem has not been solved.
A need therefore exists for methodology enabling a gate first HKMG stack integration without the possibility of formation of the metal/Si dielectric interface.